Floating point IDAC

ABSTRACT

Circuits and methods to convert a digital floating-point number into an analog current have been achieved. The conversion is performed directly by using an exponential current digital-to-analog converter (DAC) and a cascaded linear current digital-to-analog converter (DAC). The exponential current DAC is converting exponentially the exponent of the floating-point number, its output current is biasing the linear DAC, which is converting the mantissa of the floating-point number. The output current of the linear current DAC is correlates linearly with the value of the floating-point number. This technique is commutative, this means the sequence of the linear and the exponential converter can be interchanged. In this case the linear converter provides a biasing current to the exponential converter. The sign bit can be considered by converting the direction of the output current of the converter. This floating-point number conversion can handle a very high dynamic range and requires a minimum of chip space.

(1) FIELD OF THE INVENTION

This invention relates generally to digital-to-analog converters, andmore particularly to a current digital-to-analog converter convertingdigital floating-point numbers directly into an analog signal.

(2) DESCRIPTION OF THE PRIOR ART

In conventional algebraic form a floating-point number is representedby:F=±M×B ^(E),wherein F represents the absolute magnitude of the floating pointnumber, M represents the mantissa portion of the number, B representsthe base of the number system (B=10 in the decimal system), and Erepresents the exponent.

There are different floating-point storage formats known. One of themost common formats is the INTEL Short Real format, also called singleprecision format, which has being standardized by the IEEE organization.As example, the short real format, having 32 bits, is shown in FIG. 1.It has 1 bit for the sign, 8 bits for the exponent and 23 bits for themantissa.

The sign of a binary floating-point number is represented by a singlebit. A “1” indicates a negative number, and a “0” indicates a positivenumber.

An example is used to describe the representation of a mantissa. Using−3.75×10⁴ as an example, the sign is negative therefore the sign bit isON. The mantissa in this example is 3.75 and the exponent is 4. Thefractional portion of the mantissa is the sum of each digit multipliedwith the power of 10:

${.75} = {\frac{7}{10} + {\frac{5}{100}.}}$

In regard to a binary floating-point representation of the example ofthe mantissa 3.75, the fractional portion of the mantissa is the sum ofsuccessive powers of 2.

${.11} = {\frac{1}{2} + {\frac{1}{4}.}}$

Combined with the left-hand side of the mantissa the binary floatingnumber looks now 11.11, which is in decimal terms 3.75.

In IEEE Short Real format the exponents are stored as 8-bit unsignedintegers with a bias of 127. The exponent is added to 127 and the sum isrepresented binary. Using the example shown above the exponent is 4.Added to 127 results in 131 and is represented by the string of10000011.

Another common format for digital floating point numbers is the IEEELong Real format, also called double precision, having 64 bits: 1 bitfor the sign, 11 bits for the exponent and 52 bits for the mantissa.

Before storing a binary floating-point number its mantissa has to benormalized. The normalization is performed in a way that only one digitappears before the decimal. The exponent expresses the number ofpositions the decimal point was moved left.

FIG. 2 prior art shows a converter 20 converting a digitalfloating-point number 21 into an analog signal 25. In prior art adigital floating point to integer converter 22 and additionally a highresolution digital-to-analog converter 24 were required to convert adigital floating point number into an analog signal. The digitalfloating point to integer converter 22 converts the digitalfloating-point number 21 into a correspondent integer number 23. Thehigh-resolution digital-to-analog converter 24 converts then in a secondstep this integer number 23 into an analog output signal 25.

It is a challenge for the designers of such solution to find lessexpensive converters to convert digital floating-point numbers intoanalog signals.

There are patents known describing the conversion of floating pointnumbers it analog signals.

U.S. Pat. No. 4,393,369 to Davies describes the digitizing of analogsignals over a wide dynamic range for a floating-point decimalconversion. The widely fluctuating input analog voltages are convertedto currents to prevent saturation of circuit elements and are, first,compared with a derived reference signal to produce positive voltages ornegative voltages if the input signal exceeds or is less than thederived reference current. The positive and negative voltages are fed toa combined floating point processing unit and microprocessor, whichgenerates two groups of digital signals. The first group isrepresentative of m mantissa increments and the second group of nsignals is indicative of the order of magnitude of the mantissacomponents. A mantissa digital-to-analog current generator and an orderof magnitude digital-to-analog current generator are coupled in serieswith respect to each other to provide the derived reference current,which is to be compared with the next sample of the input analog signal.Since the derived reference current is derived in the immediatelypreceding sample period, the newly sampled analog signal is compared asbeing greater or lesser with a still newer input sample. The first groupof digital signals indicative of the mantissa increments and the secondgroup of digital signals indicative of the order of magnitude are fedonto following circuitry to allow for example, a visual readout orfurther processing. The floating-point analog-to-digital conversion hasthe great advantage over linear, analog arithmetic conversion by beingable to handle large dynamic ranges of analog input signals.

U.S. Pat. No. 4,278,964 to Vanderford discloses a methodology andapparatus for converting wide dynamic amplitude range digital datarecorded in floating point digital word form, comprising a binary codedmantissa and a binary coded exponent, to an analog signal, oroscillogram, of selectively compressed and/or amplified dynamicamplitude range. The digital word, occupying a number of binary bitpositions, is, in algebraic form, .+−.AG.sup.E; where A represents themantissa, or argument, G represents the base, or radix, of the numbersystem used and E represents the exponent. Since the base G is constant,for example at 8, the only binary bits that need to be recorded arethose representing the mantissa A and the exponent E. In reconvertingthe digital data to analog form for making an oscillogram, or wiggletrace, it is desired to selectively amplify and/or compress the dynamicrange and, yet, at the same time avoid introducing serious distortion.The methodology employed to accomplish such reconversion is to changeeither, or both, the mantissa A and base, or radix, G in such a way thatthe dynamic range is compressed and, yet, any distortion therebyintroduced is minimal. Apparatus for performing the aforesaid changes,among other things, is disclosed.

U.S. Pat. No. 4,240,070 to Helbig et al. teaches an apparatus and methodproviding for an improvement to a system which converts wide amplituderange digital data recorded in floating point digital word form toanalog signals within a limited amplitude range. The apparatus andmethod provides for the situation wherein the digital data can representan analog signal for which on a general decrease in amplitude increasesmay be superimposed. The apparatus includes a digital/analog converterwhose reference voltage is individually determined for each sample. Thisreference voltage is taken from a saw tooth oscillator at an instant oftime determined by a delay timer, which responds to changes, withrespect to a desired average amplitude, of the actual amplitude of theconverted data.

SUMMARY OF THE INVENTION

A principal object of the present invention is to achieve a method toconvert directly a digital floating-point number to an analog current.

Another principal object of the present invention is to achieve acircuit to convert a digital floating-point number directly to an analogcurrent having a high dynamic range and requiring a minimum of chipspace.

In accordance with the objects of this invention a method to convert adigital floating-point number directly into an analog signal has beenachieved. The method invented comprises, first, to provide a linearcurrent digital-to-analog converter cascaded with an exponential currentdigital-to-analog converter. The next steps of the method invented areto split a floating-point number into its mantissa and exponent, toconvert said exponent to a current representing an analog signal of theexponent using said exponential current digital-to-analog converter, andto convert said digital floating point number into an analog current byconverting said mantissa by said linear current digital-to-analogconverter using the output current of the previous step as biasingreference current. Additionally, if required, the sign bit of thefloating-point number can define the direction of the output current viaa current direction switch block.

In accordance with the objects of the invention an alternative method toconvert a digital floating point number directly into an analog signalhas been achieved. This method invented comprises, first, to provide anexponential current digital-to-analog converter cascaded with a linearcurrent digital-to-analog converter. The following steps of this methodare to split a floating-point number into its mantissa and exponent, toconvert said mantissa to a current representing an analog signal of themantissa using said linear current digital-to-analog converter, andconvert said digital floating point number into an analog current byconverting said exponent by said exponential current digital-to-analogconverter using the output current of the previous step as biasingreference current.

In accordance with the objects of this invention a circuit to convertdigital floating-point numbers into an analog current signal has beenachieved. This circuit invented comprises, first, an exponential currentdigital-to-analog converter, having an input and an output, wherein theinput is a vector comprising the bits of the exponent of saidfloating-point number and the output is an analog current beingcorrelated to the exponential value of said exponent. Secondly theconverter comprises a linear current digital-to-analog converter havinginputs and an output, wherein the inputs comprise a vector comprisingthe mantissa of said floating point number and said analog outputcurrent of said exponential current digital-to-analog converter and theoutput comprises an analog current being linearly correlated to thevalue of said digital floating point number.

In accordance with the objects of this invention an alternative circuitto convert digital floating point numbers into an analog current signalhas been achieved. This alternative circuit comprises, first, a linearcurrent digital-to-analog converter, having an input and an output,wherein the input is a vector comprising the bits of the mantissa ofsaid floating point number and the output is an analog current beingcorrelated to the linear value of said mantissa. Furthermore thisalternative circuit comprises an exponential current digital-to analogconverter having inputs and an output, wherein the inputs comprise avector describing the exponent of said floating-point number and saidanalog output current of said linear current digital-to-analog converterand the output comprises an analog current being linearly correlated tothe value of said digital floating point number, and, finally, a meansto convert the direction of the output current dependent upon the signof said floating-point number.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIG. 1 shows the structure of a floating-point number.

FIG. 2 prior art illustrates a block diagram of a prior artdigital-to-analog converter of a floating-point number.

FIG. 3 illustrates a block diagram of the present invention of adigital-to-analog converter of floating-point numbers.

FIG. 4 a shows a flowchart of the method invented to convert a digitalfloating-point number to an analog current.

FIG. 4 b shows a flowchart of an alternative method invented to converta digital floating-point number to an analog current.

FIG. 5 illustrates a circuit diagram of a preferred embodiment of anexponential current digital-to-analog converter of the presentinvention.

FIG. 6 illustrates a circuit diagram of a of a current direction switchblock being able to convert the direction of the output currentdependent on the sign of a floating point number to be converted.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention disclose novelmethods and circuits for conversion of a floating-point number into acorresponding analog current.

FIG. 3 shows a principal block diagram of the converter 30 of thepresent invention. Instead of using a digital floating-point-to-integerconverter and additionally a high resolution digital-to-analog converteras showed in FIG. 2 prior art the conversion of the present invention isperformed directly using two cascaded current digital-to-analogconverters (IDACs). A first IDAC 31 is converting the exponent of theincoming binary floating-point number 21 and a second low resolutionlinear IDAC 32 converts the mantissa of the incoming binaryfloating-point number 21. A biasing current I₀ is flowing into theexponential IDAC 31. The input signals of this exponential IDAC 31 are(max−min+1) bits from the exponent e_(i) [max . . . min] of the incomingbinary floating-point number 21 wherein i signifies the significant bitsof the exponent ranging from the maximal (max) or most significant bit(MSB) at the left of the bit-string of the exponent to the minimum (min)or least significant bit (LSB) to the right of the exponent.Additionally, if required, the sign bit of the floating-point number 21can define the direction of the output current via a current directionswitch block 33.

The exponential IDAC converts the incoming exponent e_(i) [max . . .min] into an output current I₁:

$\begin{matrix}{{I_{1} = {I_{0} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}}},} & (1)\end{matrix}$wherein I₁ is the output current of the exponential IDAC 31, I₀ is thebiasing current of the exponential converter, e_(j) ∈ {0, 1} representthe significant bit positions of the exponent wherein i is ranging fromthe MSB bit, signified by “max” to the LSB bit, signified by “min”. Thismeans e_(j) are components of a vector of (max−min+1) bits. The outputcurrent of the exponential IDAC 31 is the biasing reference current ofthe low resolution linear IDAC 32.

The low resolution linear IDAC 32 converts the mantissa of the incomingdigital floating-point number 21 into binary values. Using the referencecurrent I₁ from the exponential IDAC 31

$\begin{matrix}{{I_{1} = {I_{0} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}}},} & (2)\end{matrix}$wherein I₁ represents the exponent of the incoming binary floating-pointnumber 21. The low resolution linear IDAC 32 provides the mantissavalues to the current I₁ and generates a current I representing ananalog signal converted from the incoming binary floating-point number21:

$\begin{matrix}{{I = {I_{0} \times {\prod\limits_{j = \min}^{\max}{2^{2^{j}e_{j}} \times {\sum\limits_{i = 0}^{n_{m}}{2^{i}m_{i}}}}}}},} & (3)\end{matrix}$wherein

$I_{0} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}$corresponds to the output current I₁ of the exponential IDAC 31, mrepresents the mantissa of the incoming digital floating point number21, and m_(i) ∈ {0, 1} represent the bit positions of the mantissawherein i is ranging from zero position to the maximum n_(m) position ofthe mantissa. This means m_(i) are components of a vector of n_(m)+1bits.

The output current I of the converter 30 of the present inventionrepresents an analog output signal converted from an incoming digitalfloating-point number 21. According to the sign bit the currentdirection switch block 33 controls the direction of the output current Idependent upon the sign bit of the incoming floating point number; theoutput current is either sunk or sourced.

It has to be understood that the sequence of blocks 31 and 32 iscommutative. This means that the sequence of blocks 31 and 32 can beinterchanged in an alternative embodiment of the invention. In this casethe conversion of the mantissa, performed by the linear IDAC of block 32provides the biasing current for the exponential IDAC of block 31,performing the conversion of the exponent. The output of the exponentialIDAC 31 can then be used for the current direction switch of block 33according to the sign bit of the incoming floating point number.

One key advantage of the present invention is that a conversion from afloating-point number to an integer number prior to digital-to analogconversion is no more required. The cascaded digital-to-analog converterof the present invention has a high dynamic range and requires less chiparea than prior art solutions.

FIG. 4 a illustrates the method steps of a preferred embodiment of thepresent invention. Step 40 describes the provision of a linear currentdigital-to-analog converter cascaded with an exponential currentdigital-to-analog converter. In step 41 an incoming floating-pointnumber is split into its mantissa and exponent. In step 42 said exponentof the incoming floating point number is converted to a currentrepresenting an analog signal of the exponent using said exponentialcurrent digital-to-analog converter and in step 43 said digital floatingpoint number is converted into an analog current by converting saidmantissa by said linear current digital-to-analog converter using theoutput current of the previous step as biasing reference current. Ifrequired the direction of the output current can be set in step 44dependent upon the sign bit as described above. This can be advantageousfor some applications.

FIG. 4 b illustrates the method steps of an alternative embodiment ofthe present invention. As described above, according to the commutativeproperty of the present invention, the sequence of the linear andexponential conversion can be interchanged. In this alternativeembodiment the output current of a linear IDAC is used as a biasingcurrent of an exponential IDAC. Step 400 of FIG. 4 b describes theprovision of an exponential current digital-to-analog converter cascadedwith a linear current digital-to-analog converter. In step 410 anincoming floating-point number is split into its mantissa and exponent.In step 420 said mantissa of the incoming floating point number isconverted to a current representing an analog signal of the mantissausing said linear current digital-to-analog converter and in step 430said digital floating point number is converted into an analog currentby converting said exponent by said exponential currentdigital-to-analog converter using the output current of the previousstep as biasing reference current. If required the direction of theoutput current can be set in step 440 dependent upon the sign bit asdescribed above. This can be advantageous for some applications.

FIG. 5 shows a schematic of the circuit of a preferred embodiment of a4-bit exponential current digital-to analog converter 50. The converter50 shown in FIG. 5 corresponds to the converter 30 as shown in FIG. 3and is an important part of the present invention. It has to beunderstood that by cascading the circuit of FIG. 5 more bits could beexponentially converted to an analog current and vice versa less bitscan be converted by omitting some stages.

The current source 51 provides the biasing current I₀ for the converter50 according to I₀ of equation (1)

According to the block diagram of FIG. 3 the output current of theconverter 50 shown in FIG. 5 is I₁.

The gate of transistor N12 is the inverted port of the LSB bit e⁻² ofthe exponent of the floating-point number to be converted. The gate oftransistor N22 is the port of the bit e⁻¹, which is the second bit fromthe right of the exponent of the floating-point number to be converted.The gate of transistor P12 is the port of the bit e₀, which is the thirdbit from the right of the exponent of the floating-point number to beconverted and the gate of transistor P22 is the inverted port of the MSBbit e₊₁ of the exponent of the floating-point number to be converted.The indices of the four bits of the exponent range from a minimum valueof −2 to a maximum value +1 in order to match with equation (1) shownabove in case the four bits of the exponent is all zero.

The transistors N10 and N20 form a current mirror wherein N10 is theinput transistor and N20 is the output transistor. Transistor N11 can beswitched in parallel to transistor N10 by switching N12 ON by the LSBbit e⁻² of the exponent to be converted. Transistor N21 can be switchedin parallel to transistor N20 by switching transistor N22 ON by the e⁻¹bit of the exponent. Dependent upon the status of the bits e⁻² and e⁻¹the transistors of the current mirror N10/N20 can be made wider and thusthe related current mirror ratio can be changed.

The ratio R_(M) of current mirror N10/N20 ratio is

${R_{M} = {\frac{I_{o1}}{I_{in}} = \frac{L\; 10 \times W\; 20}{W\; 10 \times L\; 20}}},$wherein W10 is the width and L20 is the length of the input transistorN10, W20 is the width and L20 is the length of the output transistor N20and I_(IN) is the input current and I_(o1) is the output current of thecurrent mirror N10/N20.

For technological reasons the length of the transistors in currentmirrors is usually kept the same so only the width of the transistorshas to be considered now. The relative width of the transistors N10,N11, N20, and N21 of the NMOS current mirror configuration and therelative width of the transistors P10, P11, P20, and P21 of the PMOScurrent mirror configuration is also shown in FIG. 5. Transistor N11 hasthe width ofW _(N11)=(2² ^(j) −1)×W _(N10),wherein W_(N11) is the width of transistor N11, W_(N10) is the width oftransistor N10, and index j corresponds to the position of the relatedbit of the exponent, namely in the case of transistor N11 j correspondsto the LSB bit of the exponent having the position −2 as describedabove. This means transistor N11 has the widthW _(N11)=(2^(0.25)−1)×W _(N10).

Accordingly transistor N21 has the width ofW _(N21)=(2² ^(j) −1)×W _(N20),wherein W_(N21) is the width of transistor N21, W_(N) ₂₀ is the width oftransistor N20, and the index j corresponds to the position of therelated bit of the exponent, namely in the case of transistor N21 jcorresponds to the second bit from the right having the position −1 asdescribed above. This means transistor N11 has the widthW _(N11)=(2^(0.5)−1)×W _(N10).

In the preferred embodiment described transistor N20 has a relativewidth of 1 and transistor N10 has a relative width W_(N10)=2^(−0.2 5).Other relationships of the width of transistors N10, and N20 arepossible as well to provide a scaling of the output current. But therelationships of the pairs (N10, N11) and (N20, N21) have to accord tothe formulas above.

By switching N12 and/or N22 ON and OFF the width of N10 and N20 will bechanged and accordingly the ratio of the current mirror N10/N20 will bechanged.

In case transistor N12 is switched on by the LSB bit e⁻² and transistorN21 is still switched off, the width of the input transistor N10 of thecurrent mirror N10/N20 will be increased and the output current will bereduced by the factor 2^(−0.25).

In case transistor N22 is switched on by the LSB bit e⁻¹ the width ofthe output transistor N20 of the current mirror N10/N20 will beincreased and the output current will be increased by the factor2^(0.5).

Following is a table of the ratio of the N10/N20 current mirror as afunction of the bits e⁻¹ and e⁻² of the exponent of the incomingfloating point number

e⁻¹ e⁻² current mirror ratio 0 0 1 0 1$\frac{2^{0.5}}{2^{0.25}} \approx 1.19$ 1 0 2^(0.5) ≈ 1.41 1 12^(0.5)2^(0.25) ≈ 1.68

The current mirror P10/P20 operates principally the same way as thecurrent mirror N10/N20 described above. The bit e₀ can switch OFFtransistor P12 and thus decreases the width of the input transistor P10of the current mirror P10/P20. The inverted bit e₁ can switch OFFtransistor P22 and thus decreases the width of the output transistor P20of the current mirror P10/P20. As shown in FIG. 5 the signal of bit e₁is inverted.

Following is a table of the ratio of the P10/P20 current mirror as afunction of the bits e₀ and the inverted bit e_(1inv) of the exponent ofthe incoming floating point number

e₁ e₀ current mirror ratio 0 0 1 0 1 2 1 0 4 1 1 8The output current I₁ of the 4 bit exponential current digital-to-analogconverter 50 of the present invention shown in FIG. 5 is I_(n) times theproduct of the current mirror ratios of both N10/N20 and P10/P20mirrors.

It is obvious that in the circuit of FIG. 5 the NMOS transistors N10 toN12 and N20 to N22 could be replaced by PMOS transistors whileconcurrently replacing accordingly the PMOS transistors P10 to P12 andP20 to P22 by NMOS transistors. All inputs e_(i) would have to beinverted.

It has to be understood that the 4-bit exponential digital-to-analogconverter is an example of the present invention. More or less bits arefeasible by cascading more stages (or current mirrors) or omitting somestages. The ratios of the current mirrors must be of the form 2² ^(i) ,wherein i is an integer number.

Therefore the width of the switchable transistors (like N11, N21, P11,and P21) of the current mirrors to increase the width of thecorrespondent transistor of the current mirror has to be 2² ^(i) −1related to the width of the correspondent transistor of a currentmirror, wherein i is the index of the according bit of the inputexponent vector.

In case of an exponent having n-bits the required number N_(ST) ofstages, or in other words current mirrors corresponds to the integernumber of the division:

$N_{ST} = {{{int}\left( \frac{n + 1}{2} \right)}.}$

As described above for each bit of the exponent a transistor switch anda transistor, which is in parallel to an input or output transistor of acurrent mirror is required. Said transistor switch can switch ON thetransistor being parallel to a current mirror transistor to increase thewidth of said current mirror transistor and thus to modify the ratio ofthis current mirror. The current mirrors are deployed using by turnsNMOS and PMOS technology for each stage.

In case of an exponent having an odd number of bits one switchingtransistor and the related extension transistor is omitted. In case ofan exponent having an odd number of bits there are two alternativespossible. In a first alternative transistor switch N12 and itscorrespondent mirror extension transistor N11 will be omitted andtransistors N20 and N10 will have a same size.

Another alternative is to omit the current switch N22 and thecorrespondent current extension transistor N21.

As shown already in FIG. 3 the output current I₁ of the exponentialdigital-to-analog converter 50, as shown also in FIG. 5, is fed into astandard linear current digital-to-analog converter 32 which isconverting the mantissa of the incoming digital floating point number.This linear current digital-to-analog converter 32 can be a lowresolution DAC. The output current I₁ is biasing the linear currentdigital-to-analog converter 32. Therefore the output current I of thelinear current digital-to-analog converter 32 is an analog signaldirectly correlated to the incoming digital floating-point number.

Alternatively, as described already in FIG. 4 b, the sequence of thelinear digital-to-analog converter and of the exponentialdigital-to-analog converter can be interchanged. This means that theoutput current of said standard linear digital-to-analog converter,which is converting the mantissa of the floating point number, is fedinto the exponential current digital-to-analog converter, which isconverting the exponent of the floating point number using the outputcurrent of the linear converter as biasing current.

In both embodiments described above the sign bit of the mantissa is notconsidered because it was not required by a related application. FIG. 6illustrates how to consider the sign bit of an incoming floating-pointnumber. Dependent upon the sign bit of the incoming floating pointnumber the output current I_(SIGN) is either sunk or sourced. Current Iis the output current of the linear IDAC as shown in FIG. 3. Bothswitches S_(SI) are controlled in parallel by the sign bit of theincoming floating point number. Dependent upon the position of theswitches S_(SI) the direction of the output current I_(SIGN) remainsunchanged compared to current I or the current I is directed throughcurrent mirror M and the output current I_(SIGN) has a oppositedirection compared to current I.

One key advantage of the present invention is that the floating pointnumber is directly converted into an analog current and no digitalfloating-point to integer conversion is necessary. For an applicationwith a high dynamic range and a medium accuracy the solution inventedrequires less chip area than a high resolution DAC, required in priorart.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. A method to convert a digital floating point number directly into ananalog signal is comprising: provide a linear current digital-to-analogconverter cascaded with an exponential current digital-to-analogconverter; split a floating-point number into its mantissa and exponent;convert said exponent to a current representing an analog signal of theexponent using said exponential current digital-to-analog converterwherein the output current of said exponential current digital-to-analogconverter corresponds to the equation:${I_{1} = {I_{0} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}}},$wherein I₁ is the output current of the exponentialdigital-to-exponential converter, I₀ is a biasing current, e_(i) ∈ {0,1} represent the significant bit positions of the exponent wherein i isranging from the MSB bit, signified by “max” to the LSB bit, signifiedby “min”; and convert said digital floating point number into an analogcurrent by converting said mantissa by said linear currentdigital-to-analog converter using the output current of the previousstep as biasing reference current.
 2. The method of claim 1 wherein saidanalog signal of the exponent is a current.
 3. The method of claim 1wherein the direction of the output current indicates the sign of saidfloating-point number.
 4. The method of claim 3 wherein said change ofdirection of the output current is provided by a current mirror andswitches controlled by said sign.
 5. The method of claim 1 wherein bitsof said exponent are modifying the width of current mirror transistorswithin said exponential current digital-to-analog converter and thusamplifying or decreasing analog currents.
 6. The method of claim 5wherein the width of input and output transistors of said currentmirrors is modified.
 7. The method of claim 5 wherein said modificationof the width of transistors is performed by activating or deactivatingtransistors arranged in parallel to said current mirror transistors. 8.The method of claim 7 wherein the widths of said transistors arranged inparallel to said current mirror transistors must follow the form 2² ^(j)−1 related to the width of the transistors of the current mirror,wherein i is the index of the according bit of the vector of saidexponent.
 9. The method of claim 5 wherein said ratios of said currentmirrors must follow the form 2² ^(j) wherein j is the index of theaccording bit of the vector of said exponent.
 10. The method of claim 1wherein the output current I of said a linear current digital-to-analogconverter corresponds to the equation:${I = {I_{0} \times {\prod\limits_{j = \min}^{\max}{2^{2^{j}e_{j}} \times {\sum\limits_{i = 0}^{n_{m}}{2^{i}m_{i}}}}}}},$wherein $I_{0} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}$corresponds to the output current I₁ of said exponential currentdigital-to-analog converter, m represents the mantissa of the incomingdigital floating point number 21, and m_(i) ∈ {0, 1} represent the bitpositions of the mantissa wherein i is ranging from a minimum positionto the maximum n_(m) position of the mantissa.
 11. A method to convert adigital floating point number directly into an analog signal iscomprising: provide an exponential current digital-to-analog convertercascaded with a linear current digital-to-analog converter; split afloating-point number into its mantissa and exponent; convert saidmantissa to a current representing an analog signal of the mantissausing said linear current digital-to-analog converter wherein the outputcurrent of said linear current digital-to-analog converter correspondsto the equation:${I_{1} = {I_{0} \times {\sum\limits_{i = 0}^{n_{m}}{2^{i}m_{i}}}}},$wherein I₁ is the output current of said linear digital-to-exponentialconverter, I₀ is a biasing current, m represents the mantissa of theincoming digital floating point number, and m_(i) ∈ {0, 1} represent thebit positions of the mantissa wherein i is ranging from a minimumposition to the maximum n_(m) position of the mantissa; and convert saiddigital floating point number into an analog current by converting saidexponent by said exponential current digital-to-analog converter usingthe output current of the previous step as biasing reference current.12. The method of claim 11 wherein said analog signal of the mantissa isa current.
 13. The method of claim 11 wherein the direction of theoutput current indicates the sign of said floating-point number.
 14. Themethod of claim 13 wherein said change of direction of the outputcurrent is provided by a current mirror and switches controlled by saidsign.
 15. The method of claim 11 wherein the output current I of said aexponential current digital-to-analog converter corresponds to theequation:${I = {I_{0} \times {\sum\limits_{i = 0}^{n_{m}}{2^{i}m_{i} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}}}}},$wherein $I_{0} \times {\sum\limits_{i = 0}^{n_{m}}{2^{i}m_{i}}}$corresponds to the output current I₁ of said linear currentdigital-to-analog converter, e_(j) ∈ {0, 1} represent the significantbit positions of the exponent wherein i is ranging from the MSB bit,signified by “max” to the LSB bit, signified by “min”.
 16. The method ofclaim 11 wherein bits of said exponent are modifying the width ofcurrent mirror transistors within said exponential currentdigital-to-analog converter and thus amplifying or decreasing analogcurrents.
 17. The method of claim 16 wherein the width of input andoutput transistors of said current mirrors is modified.
 18. The methodof claim 16 wherein said modification of the width of transistors isperformed by activating or deactivating transistors arranged in parallelto said current mirror transistors.
 19. The method of claim 18 whereinthe widths of said transistors arranged in parallel to said currentmirror transistors must follow the form 2² ^(j) −1 related to the widthof the transistors of the current mirror, wherein i is the index of theaccording bit of the vector of said exponent.
 20. The method of claim 16wherein said ratios of said current mirrors must follow the form 2² ^(j), wherein j is the index of the according bit of the vector of saidexponent.
 21. A circuit to convert digital floating point numbers intoan analog current signal is comprising: an exponential currentdigital-to-analog converter, having an input and an output, wherein theinput is a vector comprising the bits of the exponent of said floatingpoint number and the output is an analog current being correlated to theexponential value of said exponent wherein the output current of saidexponential current digital-to-analog converter corresponds to theequation:${I_{1} = {I_{0} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}}},$wherein I₁ is the output current of the exponentialdigital-to-exponential converter, I₀ is a biasing current, e_(i) ∈ {0,1} represent the significant bit positions of the exponent wherein i isranging from the MSB bit, signified by “max” to the LSB bit, signifiedby “min”; a linear current digital-to analog converter having inputs andan output, wherein the inputs comprise a vector comprising the mantissaof said floating-point number and said analog output current of saidexponential current digital-to-analog converter and the output comprisesan analog current being linearly correlated to the value of said digitalfloating point number; and a means to convert the direction of theoutput current dependent upon the sign of said floating-point number.22. The circuit of claim 21 wherein said linear currentdigital-to-analog converter is a low-resolution linear currentdigital-to-analog converter.
 23. The circuit of claim 21 wherein theoutput current I of said a linear current digital-to-analog convertercorresponds to the equation:${I = {I_{0} \times {\prod\limits_{j = \min}^{\max}{2^{2^{j}e_{j}} \times {\sum\limits_{i = 0}^{n_{m}}{2^{i}m_{i}}}}}}},$wherein $I_{0} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}$corresponds to the output current I₁ of said exponential currentdigital-to-analog converter, m represents the mantissa of the incomingdigital floating point number 21, and m_(i) ∈ {0, 1} represent the bitpositions of the mantissa wherein i is ranging from a minimum positionto the maximum n_(m) position of the mantissa.
 24. The circuit of claim21 wherein said means to convert the direction of the output currentcomprises a means to mirror said output current and an arrangement ofswitches activated the sign of said floating-point number.
 25. Thecircuit of claim 24 wherein said means to convert the direction of theoutput current is comprising: a first switch, controlled by said signbit, wherein a first terminal of said switch is connected to said outputof said linear converter and a second terminal is connected to an inputtransistor of a current mirror; said input transistor of said currentmirror wherein the drain of said input transistor is connected to saidsecond terminal of said first switch and to its gate, its source isconnected to VSS voltage and its gate is connected to the gate of anoutput transistor of said current mirror; said output transistor of saidcurrent mirror wherein the drain of said output transistor is connectedto a second terminal of a second switch and its source is connected toVSS voltage; and said second switch, controlled by said sign bit,switching between a first terminal being connected to said output ofsaid linear converter and said second terminal, wherein its midpointprovides an output current of an direction controlled by said sign bit.26. The circuit of claim 21 wherein said exponential current digital-toanalog converter, being capable to convert n bits of an exponent of anincoming digital floating point number is comprising: a current source,providing a biasing current having two terminals, wherein a firstterminal is connected to VDD voltage and a second terminal is connectedto the drain of a first NMOS transistor switch, to the drain and to thegate of an NMOS input transistor of a first current mirror, to the gateof an NMOS output transistor of said first current mirror, to the gateof a second NMOS transistor being parallel to said input transistor ofsaid first current mirror, and to the gate of a third NMOS transistorbeing parallel to said output transistor of said first current mirror; anumber of stages, wherein said number of stages is correlated to thenumber of bits of said exponent and each stage is deployed by turnsusing NMOS and PMOS technology and each stage is comprising a currentmirror, two transistors, wherein each of them is arranged in parallel toeither the input or the output transistor of said current mirror, andtwo transistor switches, wherein one of said transistor switches isconnected to one of said transistors arranged in parallel to one of saidinput or output transistors, wherein each of said transistor switcheshaving their gates connected to one specific bit of said exponent andthey are activating, upon the status of the related bit of saidexponent, the corresponding transistor arranged in parallel of the inputtransistor, wherein the gate of a first transistor switch of the firstcurrent mirror is connected to the least significant bit of saidexponent and each following transistor switch has its gate connected tothe next bit of the exponent from right to left, wherein the sources ofthe NMOS current mirrors and of the related parallel transistors areconnected to Vss voltage and their gates are all interconnected, whereinthe sources of the PMOS current mirrors and of the related paralleltransistors are connected to VDD voltage and their gates are allinterconnected, wherein the output current of a current mirror is theinput current of the current mirror of the following stage with theexception of the last stage, wherein its output current is the output ofthe exponential digital-to analog converter.
 27. The circuit of claim 26wherein in case of an odd number of bits of the exponent a second ofsaid transistor switches and a second of said transistors arranged inparallel to one of said input or output transistors are being omitted.28. The circuit of claim 26 wherein in case of an odd number of bits ofthe exponent a first of said transistor switches and a first of saidtransistors arranged in parallel to one of said input or outputtransistors are being omitted.
 29. The circuit of claim 26 wherein saidnumber of stages is defined by the equation${{NST} = {{int}\left( \frac{n + 1}{2} \right)}},$ wherein NST is thenumber of stages deployed and n is the number of bits of the exponent.30. The circuit of claim 26 wherein the widths of said transistorsarranged in parallel to said current mirror transistors must follow theform 2² ^(j) −1 related to the width of the transistors of the currentmirror, wherein i is the index of the according bit of the vector ofsaid exponent.
 31. The circuit of claim 26 wherein said ratios of saidcurrent mirrors must follow the form 2² ^(j) , wherein i is the index ofthe according bit of the vector of said exponent.
 32. A circuit toconvert digital floating point numbers into an analog current signal iscomprising: a linear current digital-to-analog converter, having aninput and an output, wherein the input is a vector comprising the bitsof the mantissa of said floating point number and the output is ananalog current being correlated to the linear value of said mantissa; anexponential current digital-to analog converter having inputs and anoutput, wherein the inputs comprise a vector comprising the exponent ofsaid floating-point number and said analog output current of said linearcurrent digital-to-analog converter and the output comprises an analogcurrent being linearly correlated to the value of said digital floatingpoint number, wherein the output current I of said exponential currentdigital-to-analog converter corresponds to the equation:${I = {I_{0} \times {\sum\limits_{i = 0}^{n_{m}}{2^{i}m_{i} \times {\prod\limits_{j = \min}^{\max}2^{2^{j}e_{j}}}}}}},$wherein $I_{0} \times {\sum\limits_{i = 0}^{n_{m}}{2^{i}m_{i}}}$corresponds to the output current I₁ of said linear currentdigital-to-analog converter, m represents the mantissa of the incomingdigital floating point number 21, m_(i) ∈ {0, 1} represent the bitpositions of the mantissa wherein i is ranging from a minimum positionto the maximum n_(m) position of the mantissa, e_(j) ∈ {0, 1} representthe significant bit positions of the exponent wherein i is ranging fromthe MSB bit, signified by “max” to the LSB bit, signified by “min”; anda means to convert the direction of the output current dependent uponthe sign of said floating-point number.
 33. The circuit of claim 32wherein said linear current digital-to-analog converter is alow-resolution linear current digital-to-analog converter.
 34. Thecircuit of claim 32 wherein said means to convert the direction of theoutput current comprises a means to mirror said output current and anarrangement of switches activated the sign of said floating-pointnumber.
 35. The circuit of claim 34 wherein said means to convert thedirection of the output current is comprising: a first switch,controlled by said sign bit, wherein a first terminal of said switch isconnected to said output of said linear converter and a second terminalis connected to an input transistor of a current mirror; said inputtransistor of said current mirror wherein the drain of said inputtransistor is connected to said second terminal of said first switch andto its gate, its source is connected to VSS voltage and its gate isconnected to the gate of an output transistor of said current mirror;said output transistor of said current mirror wherein the drain of saidoutput transistor is connected to a second terminal of a second switchand its source is connected to VSS voltage; and said second switch,controlled by said sign bit, switching between a first terminal beingconnected to said output of said linear converter and said secondterminal, wherein its midpoint provides an output current of andirection controlled by said sign bit.
 36. The circuit of claim 32wherein said exponential current digital-to analog converter, beingcapable to convert n bits of an exponent of an incoming digital floatingpoint number is comprising: a current source, providing a biasingcurrent having two terminals, wherein a first terminal is connected toVDD voltage and a second terminal is connected to the drain of a firstNMOS transistor switch, to the drain and to the gate of an NMOS inputtransistor of a first current mirror, to the gate of an NMOS outputtransistor of said first current mirror, to the gate of a second NMOStransistor being parallel to said input transistor of said first currentmirror, and to the gate of a third NMOS transistor being parallel tosaid output transistor of said first current mirror; a number of stages,wherein said number of stages is correlated to the number of bits ofsaid exponent and each stage is deployed by turns using NMOS and PMOStechnology and each stage is comprising a current mirror, twotransistors, wherein each of them is arranged in parallel to either theinput or the output transistor of said current mirror, and twotransistor switches, wherein one of said transistor switches isconnected to one of said transistors arranged in parallel to one of saidinput or output transistors, wherein each of said transistor switcheshaving their gates connected to one specific bit of said exponent andthey are activating, upon the status of the related bit of saidexponent, the corresponding transistor arranged in parallel of the inputtransistor, wherein the gate of a first transistor switch of the firstcurrent mirror is connected to the least significant bit of saidexponent and each following transistor switch has its gate connected tothe next bit of the exponent from right to left, wherein the sources ofthe NMOS current mirrors and of the related parallel transistors areconnected to Vss voltage and their gates are all interconnected, whereinthe sources of the PMOS current mirrors and of the related paralleltransistors are connected to VDD voltage and their gates are allinterconnected, wherein the output current of a current mirror is theinput current of the current mirror of the following stage with theexception of the last stage, wherein its output current is the output ofthe exponential digital-to analog converter.
 37. The circuit of claim 36wherein in case of an odd number of bits of the exponent a second ofsaid transistor switches and a second of said transistors arranged inparallel to one of said input or output transistors are being omitted.38. The circuit of claim 36 wherein in case of an odd number of bits ofthe exponent a first of said transistor switches and a first of saidtransistors arranged in parallel to one of said input or outputtransistors are being omitted.
 39. The circuit of claim 36 wherein saidnumber of stages is defined by the equation${{NST} = {{int}\mspace{11mu}\left( \frac{n + 1}{2} \right)}},$ whereinNST is the number of stages deployed and n is the number of bits of theexponent.
 40. The circuit of claim 36 wherein the widths of saidtransistors arranged in parallel to said current mirror transistors mustfollow the form 2² ^(j) −1 related to the width of the transistors ofthe current mirror, wherein i is the index of the according bit of thevector of said exponent.
 41. The circuit of claim 36 wherein said ratiosof said current mirrors must follow the form 2² ^(j) , wherein i is theindex of the according bit of the vector of said exponent.